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IPC TM-650 2.6.3.5
Bare Board Cleanliness by Surface Insulation Resistance
| contributor author | IPC - Association Connecting Electronics Industries | |
| date accessioned | 2017-09-04T17:34:24Z | |
| date available | 2017-09-04T17:34:24Z | |
| date copyright | 01/01/2004 | |
| date issued | 2004 | |
| identifier other | DFLGIBAAAAAAAAAA.pdf | |
| identifier uri | https://lib.yabesh.ir/std/handle/yse/157367 | |
| description abstract | This test method is used to characterize the cleanliness of printed wiring board fabrication processes by determining the degradation of electrical insulation resistance under conditions of high temperature and humidity. This test method examines the cleanliness of a test substrate prior to solder mask application, after solder mask application, and after any final metalization and/or surface finish operation (e.g., HASL or OSP), and may be used to demonstrate the cleanliness of internal layers of a mulitilayer board prior to lamination. | |
| language | English | |
| title | IPC TM-650 2.6.3.5 | num |
| title | Bare Board Cleanliness by Surface Insulation Resistance | en |
| type | standard | |
| page | 4 | |
| status | Active | |
| tree | IPC - Association Connecting Electronics Industries:;2004 | |
| contenttype | fulltext |
