درباره ما
JEDEC JESD8-19
POD18 - 1.8 V Pseudo Open Drain I/O
| contributor author | JEDEC - Solid State Technology Association | |
| date accessioned | 2017-09-04T18:00:35Z | |
| date available | 2017-09-04T18:00:35Z | |
| date copyright | 39052 | |
| date issued | 2006 | |
| identifier other | FXCRXBAAAAAAAAAA.pdf | |
| identifier uri | https://lib.yabesh.ir/std/handle/yse/183624 | |
| description abstract | This standard defines the dc and ac single-ended (data) and differential (clock) operating conditions, I/O impedances, and the termination and calibration scheme for 1.8 V Pseudo Open Drain I/Os. The 1.8 V Pseudo Open Drain interface, also known as POD18, is primarily used to communicate with GDDR3 SGRAM devices. | |
| language | English | |
| title | JEDEC JESD8-19 | num |
| title | POD18 - 1.8 V Pseudo Open Drain I/O | en |
| type | standard | |
| page | 14 | |
| status | Active | |
| tree | JEDEC - Solid State Technology Association:;2006 | |
| contenttype | fulltext | |
| subject keywords | DRAM | |
| subject keywords | GDDR# | |
| subject keywords | POD | |
| subject keywords | POD18 | |
| subject keywords | POD-18 | |
| subject keywords | RAM | |
| subject keywords | SGRAM |
