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JEDEC JESD82-6A
Definition of the SSTV32852 2.5-V 24-Bit to 48-Bit SSTL_2 Registered Buffer for 1U Stacked DDR DIMM Applications
| contributor author | JEDEC - Solid State Technology Association | |
| date accessioned | 2017-09-04T18:14:31Z | |
| date available | 2017-09-04T18:14:31Z | |
| date copyright | 38292 | |
| date issued | 2004 | |
| identifier other | HHTPGBAAAAAAAAAA.pdf | |
| identifier uri | https://lib.yabesh.ir/std/handle/yse/197445 | |
| description abstract | This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTV32852 24-bit to 48-bit SSTL_2 registered buffer for stacked DDR DIMM applications. The purpose is to provide a standard for the SSTV32852 logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. | |
| language | English | |
| title | JEDEC JESD82-6A | num |
| title | Definition of the SSTV32852 2.5-V 24-Bit to 48-Bit SSTL_2 Registered Buffer for 1U Stacked DDR DIMM Applications | en |
| type | standard | |
| page | 18 | |
| status | Active | |
| tree | JEDEC - Solid State Technology Association:;2004 | |
| contenttype | fulltext | |
| subject keywords | DDR | |
| subject keywords | DIMM | |
| subject keywords | Low Profile | |
| subject keywords | SDRAM | |
| subject keywords | SSTV32852 | |
| subject keywords | Stacked | |
| subject keywords | Support Logic |
