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JEDEC JEP147
Procedure for Measuring Input Capacitance Using a Vector Network Analyzer (VNA)
| contributor author | JEDEC - Solid State Technology Association | |
| date accessioned | 2017-09-04T18:50:04Z | |
| date available | 2017-09-04T18:50:04Z | |
| date copyright | 37895 | |
| date issued | 2003 | |
| identifier other | KTOBKBAAAAAAAAAA.pdf | |
| identifier uri | https://lib.yabesh.ir/std/handle/yse/231397 | |
| description abstract | This procedure describes a recommended way to measure pin capacitance of devices with SSTL (Stub Series Terminated Logic) interface pins by use of a Vector Network Analyzer. One purpose of this standard procedure is to reduce the lengthy and often inaccurate footnote - usually found around the specification of pin parasitics To a simple reference to this document. In special cases modifying statements may adjust this procedure to the special needs of certain component. | |
| language | English | |
| title | JEDEC JEP147 | num |
| title | Procedure for Measuring Input Capacitance Using a Vector Network Analyzer (VNA) | en |
| type | standard | |
| page | 11 | |
| status | Active | |
| tree | JEDEC - Solid State Technology Association:;2003 | |
| contenttype | fulltext | |
| subject keywords | Analyzer | |
| subject keywords | DDR SDRAM | |
| subject keywords | DDR2 SDRAM | |
| subject keywords | Input Capacitance | |
| subject keywords | Measurement Procedures | |
| subject keywords | SSTL_18 | |
| subject keywords | SSTL_2 | |
| subject keywords | Vector Network Analyzer |
