درباره ما
JEDEC JEB5-A
Methods of Measurement for Semiconductor Logic Gating Microcircuits
| contributor author | JEDEC - Solid State Technology Association | |
| date accessioned | 2017-09-04T16:08:43Z | |
| date available | 2017-09-04T16:08:43Z | |
| date copyright | 01/01/1970 (R 1984) | |
| date issued | 1984 | |
| identifier other | SEWNCAAAAAAAAAAA.pdf | |
| identifier uri | https://lib.yabesh.ir/std/handle/yse/71964 | |
| description abstract | The purpose of this bulletin is to recommend for use in the rating of semiconductor logic gating microcircuits which use the binary states to represent and process logic information. Both static and dynamic measurements are covered. | |
| language | English | |
| title | JEDEC JEB5-A | num |
| title | Methods of Measurement for Semiconductor Logic Gating Microcircuits | en |
| type | standard | |
| page | 44 | |
| status | Active | |
| tree | JEDEC - Solid State Technology Association:;1984 | |
| contenttype | fulltext | |
| subject keywords | Logic Gating Microcircuits | |
| subject keywords | Measurement - Static and Dynamic |
