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IPC J-STD-012
Implementation of Flip Chip and Chip Scale Technology
Organization:
IPC - Association Connecting Electronics Industries
Year: 1996
Abstract: This document describes the implementation of flip chip and related chip scale semiconductor packaging technologies. The areas discussed include: design considerations, assembly processes, technology choices, application, and reliability data. Chip scale packaging variations include: flip chip, High Density Interconnect (HDI), Micro Ball Grid Array (μBGA), Micro Surface Mount Technology (MSMT) and Slightly Larger than Integrated Circuit Carrier (SLICC).
Purpose This document is intended to provide general information on implementing flip chip and chip scale technologies for creating single chip or multichip modules (MCM), IC cards, memory cards and very dense surface mount assemblies.
Categorization Flip chip is categorized as versions of a tin-lead (SnPb) solder bump process, and alternative solutions that use other forms of chip bond site bumping.
Chip scale technology is categorized as semiconductor chip structures that have been made robust to facilitate ease of chip handling, testing and chip assembly. The chip scale technologies have common attributes of minimal size, no more than 1.2X the area of the original die size, and are direct surface mountable.
Purpose This document is intended to provide general information on implementing flip chip and chip scale technologies for creating single chip or multichip modules (MCM), IC cards, memory cards and very dense surface mount assemblies.
Categorization Flip chip is categorized as versions of a tin-lead (SnPb) solder bump process, and alternative solutions that use other forms of chip bond site bumping.
Chip scale technology is categorized as semiconductor chip structures that have been made robust to facilitate ease of chip handling, testing and chip assembly. The chip scale technologies have common attributes of minimal size, no more than 1.2X the area of the original die size, and are direct surface mountable.
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| contributor author | IPC - Association Connecting Electronics Industries | |
| date accessioned | 2017-09-04T17:02:05Z | |
| date available | 2017-09-04T17:02:05Z | |
| date copyright | 01/01/1996 | |
| date issued | 1996 | |
| identifier other | XTBMCAAAAAAAAAAA.pdf | |
| identifier uri | https://lib.yabesh.ir/std/handle/yse/125570 | |
| description abstract | This document describes the implementation of flip chip and related chip scale semiconductor packaging technologies. The areas discussed include: design considerations, assembly processes, technology choices, application, and reliability data. Chip scale packaging variations include: flip chip, High Density Interconnect (HDI), Micro Ball Grid Array (μBGA), Micro Surface Mount Technology (MSMT) and Slightly Larger than Integrated Circuit Carrier (SLICC). Purpose This document is intended to provide general information on implementing flip chip and chip scale technologies for creating single chip or multichip modules (MCM), IC cards, memory cards and very dense surface mount assemblies. Categorization Flip chip is categorized as versions of a tin-lead (SnPb) solder bump process, and alternative solutions that use other forms of chip bond site bumping. Chip scale technology is categorized as semiconductor chip structures that have been made robust to facilitate ease of chip handling, testing and chip assembly. The chip scale technologies have common attributes of minimal size, no more than 1.2X the area of the original die size, and are direct surface mountable. | |
| language | English | |
| title | IPC J-STD-012 | num |
| title | Implementation of Flip Chip and Chip Scale Technology | en |
| type | standard | |
| page | 120 | |
| status | Withdrawn | |
| tree | IPC - Association Connecting Electronics Industries:;1996 | |
| contenttype | fulltext |