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JEDEC JESD372
The Measurement of Small-Signal VHF-UHF Transistor Admittance Parameters
Organization:
JEDEC - Solid State Technology Association
Year: 2009
Abstract: General
The measuring system must provide a means for applying bias to the transistor under test. The bias system must be such as not to influence the accuracy of the measurements.
The signal applied by the measuring system to the transistor must be sufficiently small to satisfy the "small-signal conditions" defined in 1.2. In addition, any spurious signals which might appear at the transistor terminals, and in particular, the local oscillator feedthrough when a superheterodyne receiver is used, must be kept at least 20 dB* below the specified small-signal conditions.
Ideally, the measurement of an admittance parameter would require a perfect voltage source at one port and a perfect short circuit at the other. Such requirements cannot be simultaneously fulfilled in practice; measurements have to be made with finite source impedances or load admittances, or both. The schematic diagram of Fig. 3 illustrates the general case and the specifications are given below.
*All asterisks in this document refer to the following footnote:
The numerical values quoted have been agreed upon by the JS-9 JEDEC committee as those representing a practical compromise between the usual requirements of circuit design applications of admittance parameters and the meawrement technology at the time of writing this document.
The measuring system must provide a means for applying bias to the transistor under test. The bias system must be such as not to influence the accuracy of the measurements.
The signal applied by the measuring system to the transistor must be sufficiently small to satisfy the "small-signal conditions" defined in 1.2. In addition, any spurious signals which might appear at the transistor terminals, and in particular, the local oscillator feedthrough when a superheterodyne receiver is used, must be kept at least 20 dB* below the specified small-signal conditions.
Ideally, the measurement of an admittance parameter would require a perfect voltage source at one port and a perfect short circuit at the other. Such requirements cannot be simultaneously fulfilled in practice; measurements have to be made with finite source impedances or load admittances, or both. The schematic diagram of Fig. 3 illustrates the general case and the specifications are given below.
*All asterisks in this document refer to the following footnote:
The numerical values quoted have been agreed upon by the JS-9 JEDEC committee as those representing a practical compromise between the usual requirements of circuit design applications of admittance parameters and the meawrement technology at the time of writing this document.
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| contributor author | JEDEC - Solid State Technology Association | |
| date accessioned | 2017-09-04T18:41:55Z | |
| date available | 2017-09-04T18:41:55Z | |
| date copyright | 05/01/1970 (R 2009) | |
| date issued | 2009 | |
| identifier other | ALQISCAAAAAAAAAA.pdf | |
| identifier uri | https://lib.yabesh.ir/std/handle/yse/223439 | |
| description abstract | General The measuring system must provide a means for applying bias to the transistor under test. The bias system must be such as not to influence the accuracy of the measurements. The signal applied by the measuring system to the transistor must be sufficiently small to satisfy the "small-signal conditions" defined in 1.2. In addition, any spurious signals which might appear at the transistor terminals, and in particular, the local oscillator feedthrough when a superheterodyne receiver is used, must be kept at least 20 dB* below the specified small-signal conditions. Ideally, the measurement of an admittance parameter would require a perfect voltage source at one port and a perfect short circuit at the other. Such requirements cannot be simultaneously fulfilled in practice; measurements have to be made with finite source impedances or load admittances, or both. The schematic diagram of Fig. 3 illustrates the general case and the specifications are given below. *All asterisks in this document refer to the following footnote: The numerical values quoted have been agreed upon by the JS-9 JEDEC committee as those representing a practical compromise between the usual requirements of circuit design applications of admittance parameters and the meawrement technology at the time of writing this document. | |
| language | English | |
| title | JEDEC JESD372 | num |
| title | The Measurement of Small-Signal VHF-UHF Transistor Admittance Parameters | en |
| type | standard | |
| page | 18 | |
| status | Active | |
| tree | JEDEC - Solid State Technology Association:;2009 | |
| contenttype | fulltext |